1. Field of the Invention
The present invention is directed to detecting signal errors and, more particularly, to measuring and correcting timing errors in a communications signal.
2. Related Art
In some communications networks, especially with a one-to-many arrangement, it is common for one end (e.g., headend) to master the clocks used for communication functions such as symbol timing, carrier frequency, and burst timing. It is then the responsibility of a slave end to recover this clock from a transport medium, and use it for all channel timing variables. A difficulty arises if there are interruptions in the downstream traffic from the master, and therefore interruptions in the timing information that is carried in that downstream traffic. The slave will be asked to minimize any interruptions in upstream traffic as a result of this.
Normally, a phase locked loop (PLL) is used to recover and regenerate clocks at the slave based on the transported clock. This PLL needs to have a bandwidth that is wide enough to follow any excursions in frequency made by the master clock at the headend. The comparatively wide bandwidth necessitated on this PLL means that during periods of downstream outage, it can wander quickly away from the correct frequency such that by the time the outage terminates, the timing at the slave may have slipped many clock cycles away from the correct synchronization point. Even having the ability to open the feedback loop on this PLL does not obviate the problem, because the time needed to detect a loss of clock information is enough to cause this loop to misalign with correct timing.
Therefore, a need exists to develop a technology that addresses these concerns.